docs: developer_guides: designate steps 4, 5, 8, 9 as optional in module guide

[lgirdwood]

Description

This PR updates the audio module integration guide (module_integration_guide.rst) and its engineering lifecycle architecture diagram (Figure 320: module_development_lifecycle.svg) to clearly identify mandatory versus optional stages:

1. Optimization Stages (Steps 4 & 5 - Optional):
   • Step 4 (Memory Tiering & Cold Code): Optional optimization for minimizing scarce internal DSP SRAM footprint. Standard allocations work out-of-the-box during early bringup; cold-code placement (__cold) can be deferred until preparing production builds.
   • Step 5 (SIMD Vector Alignment): Optional optimization for hardware SIMD vector acceleration (Tensilica HiFi, ARM Neon/Helium, RISC-V Vector). Components can run portable scalar C reference loops initially.
2. Host Bringup, Velocity & Performance Analysis (Steps 8 & 9 - Optional):
   • Step 8 (Host Testbench): Optional verification stage for performance analysis, debugging, and accelerating development velocity by bringing up and testing audio processing and dynamic IPC controls on the host workstation at 10x-100x real-time speed before deploying to embedded DSP hardware.
   • Step 9 (Cadence xt-run): Optional stage for cycle-accurate DSP simulation, MCPS budget verification, and xt-gprof hotspot profiling before running on target silicon.
3. Figure 320 Lifecycle Diagram:
   • Added distinct badge pills for Steps 4, 5, 8, and 9 indicating optional status and purpose.
   • Marked Phase 3 Header as PHASE 3: SIMULATION & PROFILING (OPTIONAL).
   • Updated title banner subtitle to reflect the streamlined workflow.
4. Table & Section Context:
   • Added Requirement column to the implementation stages overview table.
   • Added descriptive .. note:: and .. tip:: callout boxes to Steps 4, 5, 8, and 9 explaining the optimization and velocity benefits.

Signed-off-by: Liam Girdwood liam.r.girdwood@linux.intel.com