fix: Avoid SVE codegen in SME wrapper - #1308
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The arm_gemm SME interleave wrappers are instantiated from the SVE source bucket so explicit SME and Streaming-SVE assembly can be assembled. That also allowed the compiler to auto-vectorize ordinary C++ wrapper code into non-streaming SVE instructions, which is invalid on CPUs that expose SME/SME2 without normal SVE. Split the affected wrapper into a protected SVE bucket. It keeps the existing SVE assembler target but disables compiler vectorization for the ordinary wrapper code. Normal SVE and SVE2 buckets stay unchanged, so multi-ISA builds still carry their runtime-dispatched implementations. Resolves MLCE-2015 Signed-off-by: Pablo Marquez Tello <pablo.tello@arm.com> Change-Id: Idea17eef5a0cd422c2510ba4dbe6882f33120591
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The arm_gemm SME interleave wrappers are instantiated from the SVE source bucket so explicit SME and Streaming-SVE assembly can be assembled. That also allowed the compiler to auto-vectorize ordinary C++ wrapper code into non-streaming SVE instructions, which is invalid on CPUs that expose SME/SME2 without normal SVE.
Split the affected wrapper into a protected SVE bucket. It keeps the existing SVE assembler target but disables compiler vectorization for the ordinary wrapper code. Normal SVE and SVE2 buckets stay unchanged, so multi-ISA builds still carry their runtime-dispatched implementations.
Resolves MLCE-2015
Change-Id: Idea17eef5a0cd422c2510ba4dbe6882f33120591